金年会中国官方网站

Overview

金年会中国官方网站e 金年会中国官方网站CV215 is designed to support video data conversion from LVDS input signals into V-by-One®HS signals. 金年会中国官方网站is chip can transmit 39bits video data and 3bit control signal via only a single differential cable at an LVDS clock frequency form 20MHz to 100MHz. It has two high-speed data lane and, maximum serial data rate is 3.75Gbps/lane up to 1080p/60Hz/36bits colors.

  • LVDS to V-by-One®HS Conversion
  • 6ch LVDS 2port（Dual Pixel Link）input
    　36bits/pixel
    　140-700Mbps/ch
  • V-by-One®HS 2lanes output
    　3.75Gbps（effective rate 3.0Gbps）/lane
  • Power Supply　：1.8/3.3V
  • Package：TSSOP64
  • Recommended Rx：
    　InterfaceV-by-One®
    　InterfaceV-by-One®
LVDS Data Input V-by-One®HS Output LVDS Input Clock Frequency
4ch (24bit) 1Lane 20MHz to 100MHz
4ch (24bit) x2 2Lane 20MHz to 100MHz
5ch (30bit) 1Lane 20MHz to 85MHz
5ch (30bit) x2 2Lane 20MHz to 85MHz
6ch (36bit) 1Lane 20MHz to 75MHz
6ch (36bit) x2 2Lane 20MHz to 75MHz