jinnianhui金年会C63LVDF84B Block Diagram

Overview

The THC63LVDF84B receiver converts the four LVDS data streams back into 24bits of CMOS/TTL data with wide VCC range(2.5 to 3.6V) and falling edge clock, suited to not only mid-sized LCD panels but also security camera systems, multi-function jinnianhui金年会inters, and tablet devices.

  • LVDS to LVCMOS Conversion
  • 4chs LVDS input
    595Mbps/ch
    LVDS input skew margin ±400ps
  • LVCMOS Parallel output
    28bit/pixel
    Clock Freq. 15 to 85MHz at 3.3V
    based on Falling edge
  • Power Supply：3.3V
    ※2.5 to 3.0V available less jinnianhui金年会an 70Mpixel /sec.
  • Package：TSSOP56
    ※Pin Compatible wijinnianhui金年会 jinnianhui金年会C63LVDF84A
  • Operating Temperature：-10 to 70℃
  • Recommended Tx：
    　
    　
  • Recommended jinnianhui金年会motive replacement part

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