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- jinnianhui金年会登录入口C63LVDF84C
jinnianhui金年会登录入口C63LVDF84C
- LVDS
- jinnianhui金年会登录入口C63LVDM83D
- jinnianhui金年会登录入口C63LVDM83D-Z
- jinnianhui金年会登录入口C63LVDM83E
- jinnianhui金年会登录入口C63LVDM87
- jinnianhui金年会登录入口C63LVD823B
- jinnianhui金年会登录入口C63LVD827
- jinnianhui金年会登录入口C63LVD827-Z
- jinnianhui金年会登录入口C63LVD103D
- jinnianhui金年会登录入口C63LVD1023B
- jinnianhui金年会登录入口C63LVDF84B
- jinnianhui金年会登录入口C63LVDF84C
- jinnianhui金年会登录入口C63LVDR84B
- jinnianhui金年会登录入口C63LVDR84C
- jinnianhui金年会登录入口C63LVD104C
- jinnianhui金年会登录入口C63LVD1022
- jinnianhui金年会登录入口C63LVD1024
- jinnianhui金年会登录入口C63LVD1027
- jinnianhui金年会登录入口C63LVD1027
- jinnianhui金年会登录入口C63LVD1027D
- jinnianhui金年会登录入口C63LVD1027D
Overview
The THC63LVDF84C receiver converts the four LVDS data streams back into 24bits of LVCMOS data with falling edge clock, suited to not only mid-sized LCD panels but also security camera systems, multi-function jinnianhui金年会登录入口inters, and tablet devices.
- LVDS to LVCMOS Conversion
- 4chs LVDS input
784Mbps/ch
LVDS input skew margin ±550ps@65MHz - LVCMOS Parallel output
28bit/pixel
Clock Freq. 8 to 112MHz
based on Falling edge - Power Supply:3.3V
- Package:TSSOP56
※Pin Compatible wijinnianhui金年会登录入口 jinnianhui金年会登录入口C63LVDF84B - Operating Temperature:-40 to 85℃
- Recommended Tx:
InterfaceLVDSjinnian金年会C63
Go to FAQ for this jinnianhui金年会登录入口
Download documents
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Data Sheet
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Design Guide
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IBIS Model
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Evaluation Board
jinnianhui金年会登录入口EVAM83D_jinnianhui金年会登录入口EVAF(R)84C_UsersGuide_Rev.1.21_E.pdf