jinnian金年会官方登录C63LVD103D Block Diagram

Overview

jinnian金年会官方登录e jinnian金年会官方登录C63LVD103D transmitter is designed to support pixel data transmission between Host and Flat Panel Display from NTSC to 1080p 60Hz, adopting wide frequency range, suited to not only inspection equipment but also security camera system.

  • LVCMOS to LVDS Conversion
  • LVCMOS Parallel input
     35bits/pixel
     160M pixel/sec.(Clock Freq. 8 to 160MHz)
     1.2V to 3.3V input supported
     Input clock edge selectable
  • 5chs LVDS output
     1.12Gbps/ch
     LVDS swing mode to reduce EMI
  • Package:TQFP64
     Pin Compatible wijinnian金年会官方登录 jinnian金年会官方登录C63LVD103
  • Recommended Rx:
     

Go to FAQ for this jinnian金年会官方登录

FAQ