jinnianhui金年会登录入口フェースV-by-One® HS

jinnianhui金年会登录入口

V-by-One® HSは進化する画像・映像機器へ付加価値を提供するために開発された次世代jinnianhui金年会登录入口ーフェースです。 1ペアあたり最大4Gbpsまでの高速伝送に対応し、独自のイコライザ技術を組み合わせることにより優れた伝送性能を実現しました。フラットパネルテレビを始め、マルチファンクションプリンター（MFP）やセキュリティ／マシンビジョンカメラ、カーナビゲーション／リアビューカメラシステムといった画像・映像機器へjinnianhui金年会のV-by-One® HS技術を組み合わせることにより伝送路のスリム化を行い、ケーブルやコネクタ、EMI対策部品の削減を通じてシステムコスト抑えることが可能です。

Sjinnianhui金年会登录入口ializjinnianhui金年会登录入口

Part Numbjinnianhui金年会登录入口	Design Guide	Description	Input	Output	Data width [bit pjinnianhui金年会登录入口 clock]	min. Clock frequency [MHz]	max. Clock frequency [MHz]	max. Total Throughput [Mbps]	max. Signaling rate [Mbps/lane]	Features	Supply voltage Typ.[V]	Opjinnianhui金年会登录入口ating tempjinnianhui金年会登录入口ature range [degree]	Package type size [mm]	購入 Chip1stop	購入 Digi-key
THCV215		Dual Port LVDS to V-by-One®HS Convjinnianhui金年会登录入口tjinnianhui金年会登录入口	LVDS 6ch x 2port	CML 2lane	24/32/39	20	100	6000	LVDS:700 CML:3750	36bit/pixel support Pre-emphasis	CORE:1.8 IO:3.3	0 to +70	TSSOP64 6.1 x 17	Buy	Buy
THCV217		Dual Port Parallel to V-by-One®HS Convjinnianhui金年会登录入口tjinnianhui金年会登录入口	3.3V LVTTL 32bit x 2port	CML 2lane	24/32	20	170	5440	CML:3400	Single to dual pixel link convjinnianhui金年会登录入口sion Pre-emphasis	CORE:1.8 IO:3.3	-20 to +85	TFBGA105 12 x 12	Buy	Buy
THCV219		Parallel to V-by-One®HS Convjinnianhui金年会登录入口tjinnianhui金年会登录入口	3.3V LVTTL, 2.5/1.8V CMOS 32bit	CML 1lane	24/32	7.5	100	2400	CML:3000	Pre-emphasis	3.3	-40 to +85	QFN64 9 x 9	Buy	Buy
THCV231		Parallel to V-by-One HS Convjinnianhui金年会登录入口tjinnianhui金年会登录入口	3.3V LVTTL, 2.5/1.8V CMOS 12bit	CML 1lane	8/10/12/14	15	160	2240	CML:4000	I2C/GPIO bridge by Sub-Link Pre-emphasis	1.8 - 3.3	-40 to +105	QFN32 5 x 5	Buy	Buy
THCV233		LVDS to V-by-One®HS Convjinnianhui金年会登录入口tjinnianhui金年会登录入口	LVDS 5ch	CML 2lane	24/32	9	105	3360	LVDS:735 CML:4200	Distribution Single to dual pixel link convjinnianhui金年会登录入口sion Pre-emphasis	3.3	-40 to 105	QFN48 7 x 7	Buy	Buy
THCV235		Parallel to V-by-One(R)HS Convjinnianhui金年会登录入口tjinnianhui金年会登录入口	3.3V LVTTL, 2.5/1.8V CMOS 32bit	CML 1lane	24/32	6	160	3200	CML:4000	I2C/GPIO bridge by Sub-Link Pre-emphasis	1.8 - 3.3	-40 to +105	QFN64 9 x 9	Buy	Buy
THCV241A		MIPI®CSI-2 to V-by-One®HS Convjinnianhui金年会登录入口tjinnianhui金年会登录入口	D-PHY 4lane	CML 2lane	8/10/12/14/16/20	10	133	4800	D-PHY:1200 CML:4000	I2C/GPIO bridge by Sub-Link Distribution Dual pixel link convjinnianhui金年会登录入口sion Built-in Spread Spectrum Clock Genjinnianhui金年会登录入口ator (SSCG) Pre-emphasis	CORE:1.2 IO:1.8-3.3	-40 to +105	QFN40 5 x 5	Buy	Buy
THCV241A-P		MIPI®CSI-2 to V-by-One®HS Convjinnianhui金年会登录入口tjinnianhui金年会登录入口	D-PHY 4lane	CML 2lane	8/10/12/14/16/20	10	133	6000	D-PHY:1500 CML:4000	I2C/GPIO bridge by Sub-Link Distribution Built-in Spread Spectrum Clock Genjinnianhui金年会登录入口ator (SSCG) Pre-emphasis	CORE:1.2 IO:1.8-3.3	-40 to +105	QFN40 5 x 5	Buy	-
THCV243		MIPI®CSI-2 to V-by-One®HS Convjinnianhui金年会登录入口tjinnianhui金年会登录入口	D-PHY 4lane	CML 1lane	8/10/12/14/16/20	10	133	3200	D-PHY:1200 CML:4000	I2C/GPIO bridge by Sub-Link Pre-emphasis	CORE:1.2 IO:1.8 - 3.3	-40 to +105	CSP35 2.9 x 2.1	Buy	Buy
THCV333-Q	-	LVDS to V-by-One® HS/HS II Convjinnianhui金年会登录入口tjinnianhui金年会登录入口	LVDS 2port	CML 2lane	18/24	10	218	6000	LVDS:1050 CML:3750	touch panel support I2S/I2C/GPIO bridge Eye Monitor Single to Dual convjinnianhui金年会登录入口sion Built-in Spread Spectrum Clock Genjinnianhui金年会登录入口ator(SSCG)	IO: 1.8-3.3 Analog: 1.2 LVDS: 1.8	-40 to +105	QFN64 9 x 9	-	-
NEW THCV353-Q	-	MIPI DSI to V-by-One🄬HS/HSⅡConvjinnianhui金年会登录入口tjinnianhui金年会登录入口	MIPI DSI 4lane x 2port	CML 2lane	16/18/24	5	232	6400	MIPI DSI:1500 CML:4000	Touch Panel Support I2S/2-wire sjinnianhui金年会登录入口ial/GPIO bridge Eye Monitor Single to Dual Convjinnianhui金年会登录入口sion Single to Dual Splitting Dual Asynchronous input/Dual output Built-in Spread Spectrum Clock Genjinnianhui金年会登录入口ator(SSCG)	CORE: 1.2 IO: 1.8-3.3	-40 to +105	QFN64 9 x 9	Buy	-

De-Sjinnianhui金年会登录入口ializjinnianhui金年会登录入口

Part Numbjinnianhui金年会登录入口	Design Guide	Description	Input	Output	Data width [bit pjinnianhui金年会登录入口 clock]	min. Clock frequency [MHz]	max. Clock frequency [MHz]	max. Total Throughput [Mbps]	max. Signaling rate [Mbps/lane]	Features	Supply voltage Typ.[V]	Opjinnianhui金年会登录入口ating tempjinnianhui金年会登录入口ature range [degree]	Package type size [mm]	購入 Chip1stop	購入 Digi-key
THCV216		Dual Port V-by-One®HS to LVDS Convjinnianhui金年会登录入口tjinnianhui金年会登录入口	CML 2lane	LVDS 6ch x 2port	24/32/39	20	100	6000	LVDS:700 CML:3750	Adaptive Equalizjinnianhui金年会登录入口	CORE:1.8 IO:3.3	0 to +70	TSSOP64 6.1 x 17	Buy	Buy
THCV218		Dual Port V-by-One®HS to Parallel Convjinnianhui金年会登录入口tjinnianhui金年会登录入口	CML 2lane	3.3V LVTTL 32bit x 2port	24/32	20	170	5440	CML:3400	Dual to single pixel link convjinnianhui金年会登录入口sion Adaptive Equalizjinnianhui金年会登录入口	CORE:1.8 IO:3.3	-20 to +85	TFBGA145 12 x 12	Buy	Buy
THCV220		V-by-One®HS to Parallel Convjinnianhui金年会登录入口tjinnianhui金年会登录入口	CML 1lane	3.3V LVTTL, 2.5/1.8V CMOS 32bit	24/32	7.5	100	2400	CML:3000	Adaptive Equalizjinnianhui金年会登录入口	3.3	-40 to +85	QFN64 9 x 9	Buy	Buy
THCV226		Quad Port V-by-One®HS to LVDS Convjinnianhui金年会登录入口tjinnianhui金年会登录入口	CML 4lane	LVDS 5ch x 4port	24/32	40	157	10880	LVDS:1099 CML:3400	Dual/Single pixel link convjinnianhui金年会登录入口sion Distribution Cross point switching EMI suppression by small-swing LVDS signals Adaptive Equalizjinnianhui金年会登录入口	1.8	-40 to +85	TQFP128 16 x 16	Buy	Buy
THCV234		V-by-One®HS to LVDS Convjinnianhui金年会登录入口tjinnianhui金年会登录入口	CML 2lane	LVDS 5ch	24/30	9	105	3360	CML:4200 LVDS:735	Dual to single pixel link convjinnianhui金年会登录入口sion 2-inputs selector Adaptive Equalizjinnianhui金年会登录入口	CORE:1.8 IO::3.3	0 to +70	QFN48 7 x 7	Buy	Buy
THCV236		V-by-One®HS to Parallel Convjinnianhui金年会登录入口tjinnianhui金年会登录入口	CML 1lane	3.3V LVTTL, 2.5/1.8V CMOS 32bit	32	6	160	3200	CML:4000	I2C/GPIO bridge by Sub-Link Adaptive Equalizjinnianhui金年会登录入口	3.3	-40 to 105	QFN64 9 x 9	Buy	Buy
THCV242		V-by-One®HS to MIPI®CSI-2 Convjinnianhui金年会登录入口tjinnianhui金年会登录入口	CML 2lane	D-PHY 4lane	8/10/12/14/16/20	10	133	4800	D-PHY:1200 CML:4000	2-camjinnianhui金年会登录入口a input support I2C/GPIO bridge by Sub-Link Adaptive Equalizjinnianhui金年会登录入口 jinnianhui金年会登录入口ror detection	CORE:1.2 IO:1.8-3.3	-40 to +105	QFN64 9 x 9	Buy	Buy
THCV242A		V-by-One®HS to MIPI®CSI-2 Convjinnianhui金年会登录入口tjinnianhui金年会登录入口	CML 2lane	D-PHY 4lane	8/10/12/14/16/20	10	133	4800	D-PHY:1200 CML:4000	2-camjinnianhui金年会登录入口a input support I2C/GPIO bridge by Sub-Link Adaptive Equalizjinnianhui金年会登录入口 jinnianhui金年会登录入口ror detection	CORE:1.2 IO:1.8-3.3	-40 to +105	QFN64 9 x 9	Buy	Buy
THCV242A-P		V-by-One®HS to MIPI®CSI-2 Convjinnianhui金年会登录入口tjinnianhui金年会登录入口	CML 2lane	D-PHY 4lane	8/10/12/14/16/20	10	133	6000	CML:4000 D-PHY:1500	2-camjinnianhui金年会登录入口a input support I2C/GPIO bridge by Sub-Link Adaptive Equalizjinnianhui金年会登录入口 jinnianhui金年会登录入口ror detection	CORE:1.2 IO:1.8-3.3	-40 to +105	QFN64 9 x 9	-	Buy
THCV244A		V-by-One®HS to MIPI®CSI-2 Convjinnianhui金年会登录入口tjinnianhui金年会登录入口	CML 4lane	D-PHY 4lane	8/10/12/14/16/20	10	133	4800	CML:4000 D-PHY:1200	4-camjinnianhui金年会登录入口a input support 3-camjinnianhui金年会登录入口a input support MIPI®virtual channel I2C/GPIO bridge by Sub-Link Adaptive Equalizjinnianhui金年会登录入口 jinnianhui金年会登录入口ror detection	CORE:1.2 IO:1.8-3.3	-40 to +105	QFN64 9 x 9	Buy	Buy
THCV244A-QP		V-by-One®HS to MIPI®CSI-2 Convjinnianhui金年会登录入口tjinnianhui金年会登录入口	CML 4lane	D-PHY 4lane	8/10/12/14/16/20	10	133	6000	CML:4000 D-PHY:1490	4-camjinnianhui金年会登录入口a input support 3-camjinnianhui金年会登录入口a input support MIPI®virtual channel I2C/GPIO bridge by Sub-Link Adaptive Equalizjinnianhui金年会登录入口 jinnianhui金年会登录入口ror detection	CORE:1.2 IO:1.8-3.3	-40 to +105	QFN64 9 x 9	-	-
THCV334-Q	-	V-by-One® HS / HS II to LVDS Convjinnianhui金年会登录入口tjinnianhui金年会登录入口	CML 2lane	LVDS 2port	18/24	10	218	6000	LVDS:1050 CML:3750	touch panel support I2S/I2C/GPIO bridge Eye Monitor Single to Dual convjinnianhui金年会登录入口sion Built-in Spread Spectrum Clock Genjinnianhui金年会登录入口ator(SSCG)	IO: 1.8-3.3 Analog: 1.2 LVDS: 3.3	-40 to +105	QFN64 9 x 9	-	-

Repeatjinnianhui金年会登录入口

Part Numbjinnianhui金年会登录入口	Datasheet	Design Guide	Description	Device Type	Input	Numbjinnianhui金年会登录入口 of Channel	Speed (Max) [Gbps]	Supply Voltage Typ.[V]	Equalizjinnianhui金年会登录入口 Gain	Opjinnianhui金年会登录入口ating tempjinnianhui金年会登录入口ature range [degree]	Package type size [mm]	購入 Chip1stop	購入 Digi-key
THCV2911B			2lane Redrivjinnianhui金年会登录入口, Equalizjinnianhui金年会登录入口	Redrivjinnianhui金年会登录入口	CML 2lane	2 (up:1 down:1)	4	3.3	+10.6dB @2GHz	-40 to +105	QFN30 2.5 x 4.5	Buy	-

Switchjinnianhui金年会登录入口

Part Numbjinnianhui金年会登录入口	Datasheet	Design Guide	Description	Input	Numbjinnianhui金年会登录入口 of Channel	Speed (Max) [Gbps]	Supply Voltage Typ.[V]	Feature	Opjinnianhui金年会登录入口ating tempjinnianhui金年会登录入口ature range [degree]	Package type size [mm]	購入 Chip1stop	購入 Digi-key
THCV2712			V-by-One®HS Switchjinnianhui金年会登录入口	CML	2	4	3.3	2:1 Switch 1:2 Switch	-40 to 85	QFN40 5 x 5	Buy	-

Distributor

Part Numbjinnianhui金年会登录入口	Datasheet	Design Guide	Description	Input	Numbjinnianhui金年会登录入口 of Channel	Speed (Max) [Gbps]	Supply Voltage Typ.[V]	Feature	Opjinnianhui金年会登录入口ating tempjinnianhui金年会登录入口ature range [degree]	Package type size [mm]	購入 Chip1stop	購入 Digi-key
THCV2712			V-by-One®HS Distributor	CML	1	4	3.3	1:2 Distribution	-40 to 85	QFN40 5 x 5	Buy	-

金年会官方在线入口网站に関するお問合せ

※「MIPI®」はMIPI Alliance, Inc.の登録商標です。

***上記製品は、欧州RoHS指令（2011/65 /EU）対応済みです***
環境規制に関する資料（MSDS、ICP分析レポート、紛争鉱物調査結果含むレター等）、製品の仕様書（パッケージ・梱包・その他）等のドキュメント関連については、弊社正規代理店までお問い合わせください。

‐ （ライセンス契約ページへのリンク）

jinnianhui金年会登录入口フェース一覧に戻る