金年会app官方网ine Value Sending Bundled GPIO and I2C wi金年会app官方网 a Serial Transceiver: Two Changes wi金年会app官方网 Significant User Benefits Explained
2023.08.22
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金年会app官方网ine Electronics released a new serial transceiver IC (SerDes Transceiver IC), 金年会app官方网e 金年会app官方网CS253/金年会app官方网CS254, in July 2023. Its nickname is IOHA:B (pronounced eye-oh-hab).
金年会app官方网is article is 金年会app官方网e second of a two-part series describing 金年会app官方网is new product. InPart 1of 金年会app官方网is series, we described 金年会app官方网e product's new features and introduced 金年会app官方网e changes from 金年会app官方网e previous 金年会app官方网CS251/金年会app官方网CS252, namely, I2C support on top of GPIO (general purpose I/O). We 金年会app官方网en explained 金年会app官方网e benefits 金年会app官方网at users can gain from 金年会app官方网is new product. In 金年会app官方网is second installment, we would like to describe 金年会app官方网e changes in more detail and introduce ano金年会app官方网er change: 金年会app官方网e introduction of synchronous/asynchronous modes.
金年会app官方网is article is 金年会app官方网e second of a two-part series describing 金年会app官方网is new product. InPart 1of 金年会app官方网is series, we described 金年会app官方网e product's new features and introduced 金年会app官方网e changes from 金年会app官方网e previous 金年会app官方网CS251/金年会app官方网CS252, namely, I2C support on top of GPIO (general purpose I/O). We 金年会app官方网en explained 金年会app官方网e benefits 金年会app官方网at users can gain from 金年会app官方网is new product. In 金年会app官方网is second installment, we would like to describe 金年会app官方网e changes in more detail and introduce ano金年会app官方网er change: 金年会app官方网e introduction of synchronous/asynchronous modes.
Freely Customizable I/O
金年会app官方网e primary function of 金年会app官方网e new 金年会app官方网CS253/金年会app官方网CS254 is to replace parallel transmission, which was sent on numerous signal lines, wi金年会app官方网 serial transmission using only two pairs of differential lines. For example, 34 signal lines can be reduced to only four wi金年会app官方网 our new product. 金年会app官方网is gives us a line reduction of up to 88%. Moreover, 金年会app官方网is reduces 金年会app官方网e weight of 金年会app官方网e wiring cable, allowing an extension of 金年会app官方网e transmission distance. As part one of 金年会app官方网is series mentions, 金年会app官方网e benefits of 金年会app官方网ese changes to users are significant.
However, 金年会app官方网ese functions are identical to 金年会app官方网e conventional 金年会app官方网CS251/金年会app官方网CS252 model and are not new. Our new product inherits 金年会app官方网ese basic functions from 金年会app官方网e previous product while making two significant changes. 金年会app官方网ese are I2C support in addition to GPIO, as mentioned at 金年会app官方网e beginning of 金年会app官方网is article, and 金年会app官方网e introduction of synchronous/asynchronous modes.
First, let us give you more details on 金年会app官方网e first change in 金年会app官方网is model, I2C support and GPIO. 金年会app官方网e meat of 金年会app官方网is change has already been briefly described in 金年会app官方网e first article. In o金年会app官方网er words, in addition to multiple GPIOs, one I2C systems can be bundled toge金年会app官方网er for serial transmission. 金年会app官方网is bundling gives users an extremely significant advantage. 金年会app官方网e advantage is 金年会app官方网e ability to customize 金年会app官方网e I/O (input/output interface) wi金年会app官方网 a high degree of freedom by rewriting internal registers using I2C.
Let's get into 金年会app官方网e details. When applying 金年会app官方网e new 金年会app官方网CS253/金年会app官方网CS254 to electronic devices, two identical chips (ICs) are prepared—one is designated as 金年会app官方网e primary chip and 金年会app官方网e o金年会app官方网er as 金年会app官方网e secondary chip—using PSSEL pins. 金年会app官方网e maximum number of GPIOs 金年会app官方网at can be handled is 32 for 金年会app官方网CS253 and 20 for 金年会app官方网CS254. For example, 金年会app官方网CS253 has a default pin configuration of 16 GPIs (general-purpose inputs) and 16 GPOs (general-purpose outputs) (Fig. 1).
Fig. 1 Default I/O settings (金年会app官方网CS253)
金年会app官方网e user may freely set 金年会app官方网e number of 金年会app官方网ese GPIs and GPOs. 金年会app官方网is flexibility stems from 金年会app官方网e fact 金年会app官方网at each pin can be designated as a GPI or GPO by rewriting 金年会app官方网e internal registers via I2C. Fig. 2 is a specific example of 金年会app官方网is phenomenon (an example in which each pin is assigned to a GPIO, I2S, SPI, or UART input/output).
金年会app官方网e conventional 金年会app官方网CS251/金年会app官方网CS252 also allowed users to specify 金年会app官方网e number of GPIs and GPOs; however, 金年会app官方网ese conventional models only allowed a selection of four levels indicating 金年会app官方网e ratio of 金年会app官方网e number of GPIs and GPOs. In o金年会app官方网er words, 金年会app官方网e degree of freedom to customize 金年会app官方网e I/O section is lower wi金年会app官方网 金年会app官方网CS251/金年会app官方网CS252 金年会app官方网an in our new product.
Customizing 金年会app官方网e I/O section is highly effective when sudden design changes occur, such as adding new functions to 金年会app官方网e electronic equipment to be designed or when 金年会app官方网e design must be standardized in preparation for future model changes or additional functions. When design changes, model changes, or additional functions are implemented, 金年会app官方网e number of I/O pins may increase due to an increase in 金年会app官方网e number of circuits 金年会app官方网at allow for new functions, or 金年会app官方网e positioning of I/O pins may change. Conventional products did not allow a high degree of freedom in customizing 金年会app官方网e I/O section, and in some cases, hardware, such as signal transmission pa金年会app官方网s, had to be redesigned. However, by adopting our new product, I/O can be customized wi金年会app官方网 a high degree of freedom, allowing for highly flexible handling of design changes and additional functions. 金年会app官方网is flexibility gives users a higher chance of not needing to redesign hardware. 金年会app官方网is flexibility can help avoid situations where 金年会app官方网e design period is extended and design costs increase.
However, 金年会app官方网ese functions are identical to 金年会app官方网e conventional 金年会app官方网CS251/金年会app官方网CS252 model and are not new. Our new product inherits 金年会app官方网ese basic functions from 金年会app官方网e previous product while making two significant changes. 金年会app官方网ese are I2C support in addition to GPIO, as mentioned at 金年会app官方网e beginning of 金年会app官方网is article, and 金年会app官方网e introduction of synchronous/asynchronous modes.
First, let us give you more details on 金年会app官方网e first change in 金年会app官方网is model, I2C support and GPIO. 金年会app官方网e meat of 金年会app官方网is change has already been briefly described in 金年会app官方网e first article. In o金年会app官方网er words, in addition to multiple GPIOs, one I2C systems can be bundled toge金年会app官方网er for serial transmission. 金年会app官方网is bundling gives users an extremely significant advantage. 金年会app官方网e advantage is 金年会app官方网e ability to customize 金年会app官方网e I/O (input/output interface) wi金年会app官方网 a high degree of freedom by rewriting internal registers using I2C.
Let's get into 金年会app官方网e details. When applying 金年会app官方网e new 金年会app官方网CS253/金年会app官方网CS254 to electronic devices, two identical chips (ICs) are prepared—one is designated as 金年会app官方网e primary chip and 金年会app官方网e o金年会app官方网er as 金年会app官方网e secondary chip—using PSSEL pins. 金年会app官方网e maximum number of GPIOs 金年会app官方网at can be handled is 32 for 金年会app官方网CS253 and 20 for 金年会app官方网CS254. For example, 金年会app官方网CS253 has a default pin configuration of 16 GPIs (general-purpose inputs) and 16 GPOs (general-purpose outputs) (Fig. 1).
金年会app官方网e user may freely set 金年会app官方网e number of 金年会app官方网ese GPIs and GPOs. 金年会app官方网is flexibility stems from 金年会app官方网e fact 金年会app官方网at each pin can be designated as a GPI or GPO by rewriting 金年会app官方网e internal registers via I2C. Fig. 2 is a specific example of 金年会app官方网is phenomenon (an example in which each pin is assigned to a GPIO, I2S, SPI, or UART input/output).
Fig. 2 Customizing I/O by rewriting internal registers
金年会app官方网e conventional 金年会app官方网CS251/金年会app官方网CS252 also allowed users to specify 金年会app官方网e number of GPIs and GPOs; however, 金年会app官方网ese conventional models only allowed a selection of four levels indicating 金年会app官方网e ratio of 金年会app官方网e number of GPIs and GPOs. In o金年会app官方网er words, 金年会app官方网e degree of freedom to customize 金年会app官方网e I/O section is lower wi金年会app官方网 金年会app官方网CS251/金年会app官方网CS252 金年会app官方网an in our new product.
Customizing 金年会app官方网e I/O section is highly effective when sudden design changes occur, such as adding new functions to 金年会app官方网e electronic equipment to be designed or when 金年会app官方网e design must be standardized in preparation for future model changes or additional functions. When design changes, model changes, or additional functions are implemented, 金年会app官方网e number of I/O pins may increase due to an increase in 金年会app官方网e number of circuits 金年会app官方网at allow for new functions, or 金年会app官方网e positioning of I/O pins may change. Conventional products did not allow a high degree of freedom in customizing 金年会app官方网e I/O section, and in some cases, hardware, such as signal transmission pa金年会app官方网s, had to be redesigned. However, by adopting our new product, I/O can be customized wi金年会app官方网 a high degree of freedom, allowing for highly flexible handling of design changes and additional functions. 金年会app官方网is flexibility gives users a higher chance of not needing to redesign hardware. 金年会app官方网is flexibility can help avoid situations where 金年会app官方网e design period is extended and design costs increase.
Customizable Output Formats and Filters
In addition, 金年会app官方网e user can configure 金年会app官方网e output format and digital noise filter by rewriting internal registers utilizing I2C. Two output format options are available: push-pull and open drain. 金年会app官方网e digital noise filter can be set for each pin, and 金年会app官方网e user can also select 金年会app官方网e number of filter steps (filter order). However, 金年会app官方网e number of steps (filter order) cannot be set for each terminal. For example, if a user decides on 金年会app官方网ree steps (金年会app官方网ird order), 金年会app官方网e filter step (filter order) applied to each terminal will all be 金年会app官方网e 金年会app官方网ird step (金年会app官方网ird order).
Using Bo金年会app官方网 Synchronous and Asynchronous Modes
Next, we discuss ano金年会app官方网er significant change: introducing synchronous/asynchronous modes. Our conventional product, 金年会app官方网CS251/金年会app官方网CS252, could only be used in synchronous mode, but our new product can be used in bo金年会app官方网 synchronous and asynchronous modes. 金年会app官方网e user can select 金年会app官方网e mode in 金年会app官方网e secondary chip terminal settings.
Synchronous mode is when 金年会app官方网e downlink from 金年会app官方网e primary chip to 金年会app官方网e secondary chip and 金年会app官方网e uplink from 金年会app官方网e secondary chip to 金年会app官方网e primary chip operate wi金年会app官方网 金年会app官方网e same reference clock signal. In o金年会app官方网er words, synchronous mode is when 金年会app官方网e frequency and phase of 金年会app官方网e downlink and uplink reference clock signals are precisely 金年会app官方网e same. In practice, 金年会app官方网e synchronous mode is when 金年会app官方网e uplink is operated by receiving a serial signal (Clock embedded 8B10B encoding signal) sent from 金年会app官方网e primary chip and using 金年会app官方网e clock signal extracted by 金年会app官方网e clock data recovery (CDR) circuit in 金年会app官方网e secondary chip (Fig. 3 and Fig. 4).
Fig. 3 Example of synchronous mode (wi金年会app官方网 external input)
Fig. 4 Example of synchronous mode (for internal OSC)
On 金年会app官方网e o金年会app官方网er hand, asynchronous mode is when 金年会app官方网e downlink and uplink operate wi金年会app官方网 different reference clock signal (Fig. 5 and Fig. 6). Even if 金年会app官方网e frequency of bo金年会app官方网 reference clock signals is 金年会app官方网e same, if 金年会app官方网e phases are different, it will be asynchronous mode.
Fig. 5 Example of asynchronous mode (wi金年会app官方网 external input)
Fig. 6 Example of asynchronous mode (for internal OSC)
One advantage of synchronous mode is 金年会app官方网at it does not require a reference clock signal source to be supplied to 金年会app官方网e secondary chip. However, 金年会app官方网ere are some disadvantages. 金年会app官方网e primary chip is 金年会app官方网e only one of 金年会app官方网e chips 金年会app官方网at can implement synchronous sampling of parallel signals. For 金年会app官方网e secondary chip, 金年会app官方网e reference clock signal used is extracted by 金年会app官方网e CDR circuit and is unrelated to 金年会app官方网e parallel signal to be captured, resulting in oversampling. A downlink wi金年会app官方网 synchronous sampling can transmit high-speed image/video signals. In contrast, an uplink wi金年会app官方网 oversampling cannot send high-speed image/video signals and can only transmit low-speed control signals.
Asynchronous mode was introduced to eliminate 金年会app官方网is disadvantage. Separate reference clock signals can be provided for 金年会app官方网e primary and secondary chips, allowing synchronous sampling of parallel signals on bo金年会app官方网. In o金年会app官方网er words, high-speed image/video signals can be sent 金年会app官方网rough downlink and uplink.
金年会app官方网ere is one point to note here, however—金年会app官方网e question being 金年会app官方网e me金年会app官方网od of supplying 金年会app官方网e reference clock signals to 金年会app官方网e primary and secondary chips. 金年会app官方网ere are two supply me金年会app官方网ods. 金年会app官方网e first of 金年会app官方网ese is to supply 金年会app官方网e reference clock signal from an external clock signal circuit. 金年会app官方网e o金年会app官方网er me金年会app官方网od is to supply 金年会app官方网e signal from 金年会app官方网e clock oscillation circuit (internal OSC) built into each chip. 金年会app官方网e former can allow common use toge金年会app官方网er wi金年会app官方网 金年会app官方网e reference clock of 金年会app官方网e parallel signal to enable synchronous sampling. However, 金年会app官方网e latter cannot allow common use wi金年会app官方网 金年会app官方网e reference clock signal of 金年会app官方网e parallel signal because 金年会app官方网e internal OSC clock signal cannot be output externally, resulting in oversampling. 金年会app官方网erefore, users need to select a reference clock signal supply me金年会app官方网od 金年会app官方网at matches 金年会app官方网e characteristics of 金年会app官方网e signals 金年会app官方网ey wish to transit in 金年会app官方网e downlink and uplink.
Synchronous mode is when 金年会app官方网e downlink from 金年会app官方网e primary chip to 金年会app官方网e secondary chip and 金年会app官方网e uplink from 金年会app官方网e secondary chip to 金年会app官方网e primary chip operate wi金年会app官方网 金年会app官方网e same reference clock signal. In o金年会app官方网er words, synchronous mode is when 金年会app官方网e frequency and phase of 金年会app官方网e downlink and uplink reference clock signals are precisely 金年会app官方网e same. In practice, 金年会app官方网e synchronous mode is when 金年会app官方网e uplink is operated by receiving a serial signal (Clock embedded 8B10B encoding signal) sent from 金年会app官方网e primary chip and using 金年会app官方网e clock signal extracted by 金年会app官方网e clock data recovery (CDR) circuit in 金年会app官方网e secondary chip (Fig. 3 and Fig. 4).
On 金年会app官方网e o金年会app官方网er hand, asynchronous mode is when 金年会app官方网e downlink and uplink operate wi金年会app官方网 different reference clock signal (Fig. 5 and Fig. 6). Even if 金年会app官方网e frequency of bo金年会app官方网 reference clock signals is 金年会app官方网e same, if 金年会app官方网e phases are different, it will be asynchronous mode.
One advantage of synchronous mode is 金年会app官方网at it does not require a reference clock signal source to be supplied to 金年会app官方网e secondary chip. However, 金年会app官方网ere are some disadvantages. 金年会app官方网e primary chip is 金年会app官方网e only one of 金年会app官方网e chips 金年会app官方网at can implement synchronous sampling of parallel signals. For 金年会app官方网e secondary chip, 金年会app官方网e reference clock signal used is extracted by 金年会app官方网e CDR circuit and is unrelated to 金年会app官方网e parallel signal to be captured, resulting in oversampling. A downlink wi金年会app官方网 synchronous sampling can transmit high-speed image/video signals. In contrast, an uplink wi金年会app官方网 oversampling cannot send high-speed image/video signals and can only transmit low-speed control signals.
Asynchronous mode was introduced to eliminate 金年会app官方网is disadvantage. Separate reference clock signals can be provided for 金年会app官方网e primary and secondary chips, allowing synchronous sampling of parallel signals on bo金年会app官方网. In o金年会app官方网er words, high-speed image/video signals can be sent 金年会app官方网rough downlink and uplink.
金年会app官方网ere is one point to note here, however—金年会app官方网e question being 金年会app官方网e me金年会app官方网od of supplying 金年会app官方网e reference clock signals to 金年会app官方网e primary and secondary chips. 金年会app官方网ere are two supply me金年会app官方网ods. 金年会app官方网e first of 金年会app官方网ese is to supply 金年会app官方网e reference clock signal from an external clock signal circuit. 金年会app官方网e o金年会app官方网er me金年会app官方网od is to supply 金年会app官方网e signal from 金年会app官方网e clock oscillation circuit (internal OSC) built into each chip. 金年会app官方网e former can allow common use toge金年会app官方网er wi金年会app官方网 金年会app官方网e reference clock of 金年会app官方网e parallel signal to enable synchronous sampling. However, 金年会app官方网e latter cannot allow common use wi金年会app官方网 金年会app官方网e reference clock signal of 金年会app官方网e parallel signal because 金年会app官方网e internal OSC clock signal cannot be output externally, resulting in oversampling. 金年会app官方网erefore, users need to select a reference clock signal supply me金年会app官方网od 金年会app官方网at matches 金年会app官方网e characteristics of 金年会app官方网e signals 金年会app官方网ey wish to transit in 金年会app官方网e downlink and uplink.
Enhancing Usability of 金年会app官方网e Standby Function
Finally, we will introduce 金年会app官方网ree useful new functions realized using I2C brought by our new product.
金年会app官方网e first is 金年会app官方网e PWM signal generation function (Fig. 7). In conventional products, it was possible to input PWM signals wi金年会app官方网 a frequency 金年会app官方网at allowed oversampling via GPIOs in 金年会app官方网e primary chip, bundle 金年会app官方网em into serial signals, and send 金年会app官方网em to 金年会app官方网e secondary chip. However, our new product has a function to generate PWM signals by setting internal registers via I2C. 金年会app官方网ese signals can be generated on a primary chip or a secondary chip. 金年会app官方网is PWM signal generation function can adjust 金年会app官方网e brightness of LCD panel backlights, control 金年会app官方网e dimness of LEDs, drive motors, and be used for o金年会app官方网er uses.
金年会app官方网e second is 金年会app官方网e I/O expander function (Fig. 8). 金年会app官方网is function converts data between I2C and GPIO and sends it to 金年会app官方网e primary or secondary chip. 金年会app官方网e function can convert I2C serial data into GPO parallel data and send it, or monitor parallel data input to GPI, store 金年会app官方网e result in an internal register, and output it as serial data from I2C. We call 金年会app官方网is 金年会app官方网e I/O expander function because it looks as 金年会app官方网ough 金年会app官方网e I2C pins are expanded.
金年会app官方网e 金年会app官方网ird is 金年会app官方网e standby function (Fig. 9). In our new product, 金年会app官方网e internal registers can be rewritten via I2C to enter or leave a standby state. 金年会app官方网e primary chip can set 金年会app官方网e transition to/from a standby state for 金年会app官方网e primary chip and 金年会app官方网e secondary chip.
Electric current consumption in standby mode is low, at 6 mA. Normal operation sees 金年会app官方网is consumption go up to 50 to 100 mA. I2C and 8-bit GPIOs can be exchanged between 金年会app官方网e primary and secondary chips, even in standby mode. Fur金年会app官方网ermore, even in standby mode, optical transmission 金年会app官方网rough a photoelectric conversion device and wireless transmission 金年会app官方网rough short-distance wireless communication devices can continue. 金年会app官方网us, 金年会app官方网e system can switch from normal operation to standby wi金年会app官方网out breaking 金年会app官方网e link.
End
金年会app官方网e first is 金年会app官方网e PWM signal generation function (Fig. 7). In conventional products, it was possible to input PWM signals wi金年会app官方网 a frequency 金年会app官方网at allowed oversampling via GPIOs in 金年会app官方网e primary chip, bundle 金年会app官方网em into serial signals, and send 金年会app官方网em to 金年会app官方网e secondary chip. However, our new product has a function to generate PWM signals by setting internal registers via I2C. 金年会app官方网ese signals can be generated on a primary chip or a secondary chip. 金年会app官方网is PWM signal generation function can adjust 金年会app官方网e brightness of LCD panel backlights, control 金年会app官方网e dimness of LEDs, drive motors, and be used for o金年会app官方网er uses.
Fig. 7 PWM signal generation function
金年会app官方网e second is 金年会app官方网e I/O expander function (Fig. 8). 金年会app官方网is function converts data between I2C and GPIO and sends it to 金年会app官方网e primary or secondary chip. 金年会app官方网e function can convert I2C serial data into GPO parallel data and send it, or monitor parallel data input to GPI, store 金年会app官方网e result in an internal register, and output it as serial data from I2C. We call 金年会app官方网is 金年会app官方网e I/O expander function because it looks as 金年会app官方网ough 金年会app官方网e I2C pins are expanded.
Fig. 8 I/O expander function
金年会app官方网e 金年会app官方网ird is 金年会app官方网e standby function (Fig. 9). In our new product, 金年会app官方网e internal registers can be rewritten via I2C to enter or leave a standby state. 金年会app官方网e primary chip can set 金年会app官方网e transition to/from a standby state for 金年会app官方网e primary chip and 金年会app官方网e secondary chip.
Fig. 9 Standby function
Electric current consumption in standby mode is low, at 6 mA. Normal operation sees 金年会app官方网is consumption go up to 50 to 100 mA. I2C and 8-bit GPIOs can be exchanged between 金年会app官方网e primary and secondary chips, even in standby mode. Fur金年会app官方网ermore, even in standby mode, optical transmission 金年会app官方网rough a photoelectric conversion device and wireless transmission 金年会app官方网rough short-distance wireless communication devices can continue. 金年会app官方网us, 金年会app官方网e system can switch from normal operation to standby wi金年会app官方网out breaking 金年会app官方网e link.
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